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WM2606 Low Power 10-bit Serial Input DAC
Production Data, November 2000, Rev 1.0
FEATURES
* * * 10-bit voltage output DAC Single supply from 2.7V to 5.5V Very low power consumption (3V supply): - 900W, slow mode - 2.1mW, fast mode - 3W, standby mode DNL 0.2 LSB, INL 0.5 LSB (typical) Monotonic over Temperature DSP compatible serial interface Programmable settling time of 3s or 9s typical High impedance reference input buffer
DESCRIPTION
The WM2606 is a 10-bit voltage output, resistor string digital-toanalogue converter. It can operate with supply voltages between 2.7V and 5.5V and can be powered down under software control. Power down reduces current consumption to less than 1 A. The device has been designed for glueless interface to industry standard microprocessors and DSPs. The WM2606 is programmed with a 16-bit serial word including 4 control bits and 10 data bits. Excellent performance is delivered with a typical DNL of 0.2LSBs. Monotonicity is guaranteed over the operating temperature range. The settling time of the DAC is programmable to allow for optimisation of speed versus power dissipation. The output stage is buffered by a rail-to-rail amplifier with a gain of two, which features a Class AB output stage. The reference voltage input features a high impedance buffer which eliminates the need to keep the reference source impedance low. The WM2606 is available in an 8-pin SOIC package. Commercial (0 to 70C) and Industrial (-40 to 85C) temperature range variants are available. PACKAGE 8-pin SOIC 8-pin SOIC
* * * * *
APPLICATIONS
* * * * * Digital Servo Control Loops Industrial Process Control Battery powered instruments and controls Machine and motion control devices Digital offset and gain adjustment
ORDERING INFORMATION
DEVICE WM2606CD WM2606ID TEMP. RANGE 0 to 70C -40 to 85C
BLOCK DIAGRAM
VDD (8)
TYPICAL PERFORMANCE
0.2 AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast Mode, Load = 10kOhm/100pF 0.16
REFERENCE INPUT BUFFER REF(6) X1 DAC OUTPUT BUFFER X2 (7) OUT
DNL - Differential Non-Linearity (LSBs)
0.12
DIN (1) 16-BIT SHIFT REGISTER AND CONTROL LOGIC
data
10-BIT DAC LATCH
0.08
SCLK (2) CSB (3) FS (4)
0.04
0
-0.04
POWER-ON RESET
2-BIT CONTROL LATCH
POWERDOWN/ SPEED CONTROL
-0.08
WM2606
-0.12
(5) GND
-0.16
-0.2 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
(c)2000 Wolfson Microelectronics Ltd.
WM2606 PIN CONFIGURATION
DIN SCLK CSB FS 1 2 3 4 8 7 6 5 VDD OUT REF GND
Production Data
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 NAME DIN SCLK CSB FS GND REF OUT VDD TYPE Digital input Digital input Digital input Digital input Supply Analogue input Analogue output Supply Serial data input Serial clock input Chip select. This pin is active low. Frame synchronisation for serial input data Ground Voltage reference input DAC analogue output Positive power supply DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltage, VDD to GND Digital input voltage Reference input voltage Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) from package body for 10 seconds WM2606CD WM2606ID -0.3V -0.3V 0C -40C -65C MIN MAX 7V VDD + 0.3V VDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF pin Load resistance Load capacitance Serial clock frequency Operating free-air temperature Note: Reference input voltages greater than VDD/2 will cause clipping for large DAC codes. WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
SYMBOL VDD VIH VIL VREF RL CL fSCLK TA
TEST CONDITIONS
MIN 2.7
TYP
MAX 5.5
UNIT V V
VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V See Note
2 0.8 AGND 2 10 100 20 VDD - 1.5
V V k pF MHz C C
WM2606CD WM2606ID
0 -40
70 85
2
Production Data
WM2606
ELECTRICAL CHARACTERISTICS
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.C. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD 2k to 10k load See Note 7 No load, DAC value = 512, all digital inputs 0V or VDD VDD = 5V, VREF = 2.048V Slow Mode VDD = 5V, VREF = 2.048V Fast Mode VDD = 3V, VREF = 1.024V, Slow Mode VDD = 3V, VREF = 1.024V, Fast Mode (See Note 8) 0 0.1 VDD - 0.1 0.25 V % FS INL DNL ZCE GE PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 -80 10 10 10 0.5 0.2 1.5 1.0 10 0.6 bits LSB LSB mV % FSR dB ppm/C ppm/C SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
0.4 0.9 0.3 0.7 1
0.6 1.35 0.45 1.1
mA mA mA mA A
Power down supply current Dynamic DAC Specifications Slew rate SR DAC output 10%-90% Slow Fast See Note 9 DAC output 10%-90% Slow Fast See Note 10 DAC Code 511 to 512 fs = 400kSPS, fOUT = 1.1kHz, BW = 20kHz See Note 11
0.9 3.6
V/s V/s
Settling time
ts
9 3 10 62 60 -61 68
20 5.5
s s nV-s dB dB dB dB
Glitch energy Signal to noise ratio Signal to noise and distortion ratio Total harmonic distortion Spurious free dynamic range Reference Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN SNR SNRD THD SFDR
10 5 VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 VREF = 0.2VPP + 1.024V dc DAC code 512 Slow Fast -75
M pF dB
0.525 1.3
MHz MHz
PD Rev 1.0 November 2000
WOLFSON MICROELECTRONICS LTD
3
WM2606
Production Data
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Digital Inputs High level input current Low level input current Input capacitance Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as the digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing code 512 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates 10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 11. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs. IIH IIL CI Input voltage = VDD Input voltage = 0V 3 1 1 A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
4
Production Data
WM2606
SERIAL INTERFACE
tWL SCLK 1 tSUD DIN D15 tSUCSFS NCS tWHFS FS tSUFSCLK tSUC16FS tHD D14 D13 D12 D1 D0 2 tWH 3 4 5 15 16 tSUC16CS
Figure 1 Timing Diagram Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). SYMBOL tSUCSFS tSUFS tSUC16FS TEST CONDITIONS Setup time CSB low before falling FS edge. Setup time FS low before first falling SCLK edge. Setup time, 16 falling SCLK edge after FS low on which data bit D0 is sampled before rising edge of FS. Setup time, 16 rising SCLK edge (first after data bit D0 sampled) before CSB rising edge. If FS is used instead th of the 16 rising edge to update the DAC, this setup time is between the FS rising edge and the CSB rising edge. Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high.
th th
MIN 10 8 10
TYP
MAX
UNIT ns ns ns
tSUC16CS
10
ns
tWH tWL tSUD tHD tWHFS
25 25 8 5 20
ns ns ns ns ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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WM2606 TYPICAL PERFORMANCE GRAPHS
Production Data
0.8 AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast Mode, Load = 10kOhm/100pF 0.6
0.4 INL - Integral Non-Linearity (LSBs)
0.2
0
-0.2
-0.4
-0.6
-0.8 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
Figure 2 Integral Non-Linearity
0.4
0.4
0.35
AVDD = DVDD = 3V, VREF = 1.024V, Input Code 0
AVDD = DVDD = 5V, VREF = 2.048V, Input Code = 0
0.35
0.3
0.3
0.25
OUTPUT VOLTAGE - V
0 1 2 3 4 5 I SI NK - mA 6 7 8 9
Slow
OUTPUT VOLTAGE - V
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0 10
Fast
0 0 1 2 3 4 5 ISINK - mA 6 7 8
Slow
9
10
Fast
Figure 3 Sink Current VDD = 3V
2.06
Figure 4 Sink Current VDD = 5V
4.1
AVDD = DVDD = 3V, VREF = 1.024V, Input Code = 255
2.055
4.095
VDD = 5V, VREF = 2.048V, Input Code = 255
2.05 OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
4.09
2.045
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9
Slow
4.065
10
Fast
0
1
2
3
4
5 ISOURCE - mA
6
7
8
9
Slow
10
Fast
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
6
Production Data
WM2606
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2606 is a 10-bit, voltage output DAC operating from a single supply. The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:
= 2 VREFIN V out
INPUT 11 1111 1111 : 10 0000 0001
(
) CODE
1024
OUTPUT
2 VREF
( ) 1023
1024
:
2 VREF
( ) 511
512 1024
1024 = VREF
10 0000 0000
2 VREF
()
01 1111 1111 : 00 0000 0001 00 0000 0000
2 VREF
( ) 511
:
1024 1 1024
2 VREF
()
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10M and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
Before writing any data to the WM2606, the device must first be enabled by setting CSB to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) into the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC latch which updates the voltage output to the new level. The serial interface of the device can be used in two basic modes: * * four wire (with chip select) three wire (without chip select)
Using the chip select pin CSB (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, CSB can be tied low.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
7
WM2606
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial clock rate is:
Production Data
f SCLK max =
1 = 20MHz tWH min + tWL min
Since a data word contains 16 bits, the sample rate is limited to
f s max =
16(tWH min + tWL min )
1
= 1.25MHz
However, the DAC settling time to 10 bits accuracy limits the response time of the analogue output for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
Table 2 shows the composition of a 16 bit data word. D11-D2 contains the 10-bit data word, and D14D13 hold the programmable options. Bits D15, D12, D1 and D0 should be set to ZERO. D15 D14 D13 D12 0 SPD PWR 0 Table 2 Register Map D11 D10 D9 D8 D7 D6 D5 New DAC value (10 bits) D4 D3 D2 D1 0 D0 0
PROGRAMMABLE SETTLING TIME
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode, where typical settling time to within 0.5LSB of the final value is 3s. a ZERO puts the device into the slow mode, where typical settling time is 9s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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Production Data
WM2606
APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 7.
Output Voltage 0V Negative Offset DAC code
Figure 7 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (nonzero) output voltage.
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1F decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
9
WM2606 PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body
Production Data
DM009.B
e
B
8
5
E
H
1
4
L
D h x 45o
A
A1 -C-
C
0.10 (0.004)
SEATING PLANE
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 o o 0 8
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 o o 0 8
JEDEC.95, MS-012
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
10

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